Brain-inspired is an organization, not a biology. The 20-watt number does not come from spiking — it comes from locality, conditional compute, and recall over recompute. We have hands-on evidence, not a literature opinion: we built the direct spiking integration, and it taught us why that path doesn't pay yet.
A neuron's electrical pulse is how a wet cell sends a signal down a wet wire. Reproducing it in silicon reproduces the mechanism that was never doing the work — and needs exotic hardware to do it. Three properties actually deliver the efficiency, and none of them is it spikes.
Compute and memory in the same place. Moving a weight from DRAM costs orders of magnitude more than the multiply it feeds. This is the largest term in any real power budget.
About 2% of neurons are active at any instant. The cortex is dark almost everywhere, almost always. You don't wake the visual system to smell coffee.
Most cognition is retrieval of consolidated belief, not fresh inference. You don't re-derive that fire is hot. Recall is orders of magnitude cheaper.
The topic's own complaint is that current AI is monolithic. Its ask is a floor plan: specialized areas, arranged in a hierarchy, work routed to whichever the task needs. The transformer — which in a conventional system is the whole architecture — is 98.9% of this fabric's dense cost and the last thing consulted.
Interconnecting modules at the output end is easy. At the input end is the hard half — solved by a single deterministic character-to-waveform transducer, so a convolutional region and an algebraic region look at the same signal. It's also what makes event-driven processing possible: you can't difference what was never continuous.
Recall holds what is true, in rows a human can read, edit and delete. The transformer holds how to say it and is never the source of a fact. That's what makes skipping it safe rather than degrading — and why the honest answer is "I do not have that" instead of a confabulated near-match.
Separating knowing from saying creates a skill neither half has: speaking from a retrieved structure. Hand a model a row and expect fluent, faithful speech out the other side — that's an assumption, and it's the seam where this architecture tears first. An untrained talker will ignore the chip and answer from its weights, paraphrase it into something subtly untrue, or read it out like a database.
The corpus is a by-product of a system we already run. EMBER carves chips from conversation on the way in, so for any real exchange we can see exactly which chips were written and exactly what was said next. The pair isn't constructed, it's recorded — no labeling pass, no synthetic generation, no large model in the loop teaching a small one its confident wrongness.
| Construction | What the model must learn |
|---|---|
| full chip set → the real reply | faithful speech from structure |
| hold back a chip → the reply that used it | must no longer assert it |
| empty chip set → any question | "I do not have that." |
| low-confidence chip → the reply | hedge, do not assert |
| inherited chip → the reply | state it, and that it was inferred |
Ablating a chip and requiring the model to drop the claim it supported is the direct cure for the worst failure mode: answering from weights while pretending to answer from memory. A model trained this way can't smooth over a missing row — it saw thousands of examples of the row being missing.
Lifted from production training code where it decides per-layer precision during real runs, re-aimed at per-region allocation. Every region carries a health bar: low demand damages it, genuine work regenerates it.
Health hits zero, the region changes precision regime permanently. No flapping back — oscillating pays the switching cost forever and gets neither regime's benefit.
A region that absorbs pressure without breaking gets tougher, scaled by how close the hit came. Surviving a scare at 4 bits teaches it to shrug off what would have staggered it before.
One component sees the whole workload rather than one region, declares its phase, and sets the rules the breakers judge under. Phase changes need consecutive agreeing readings.
phase=ACTIVE step=10 salience 4b health 10.0 hits 0 hardens 0 sequence 4b health 10.0 hits 0 hardens 0 recall 4b health 10.0 hits 0 hardens 0 ontology 4b health 10.0 hits 0 hardens 0 perception 4b health 5.0 hits 5 hardens 1 association 4b health 10.0 hits 0 hardens 0 log: step 4: phase COLD -> ACTIVE (novelty 0.25)
An efficiency claim that arrives as a single benchmark number cannot be interrogated. A running health ledger can. BREAK perception at step 12 is a sentence a reviewer can read.
Every region reports the multiply-accumulates it actually performed and the precision it performed them at. The ledger charges MACs × bits — deliberately conservative, since memory traffic scales linearly with bits moved while multiply energy scales worse than linearly. If it wins under pessimistic accounting, it wins.
region MACs bits units why perception 4,200,000 4 16,800,000 feature extraction sequence 180,000 4 720,000 temporal state ontology 36,000 4 144,000 cheetah -> mammal -> animal recall 12,288 4 49,152 bind/unbind/cleanup salience 8 4 32 delta 0.00 association -- -- 0 SKIPPED: demand 0.05 below floor TOTAL 4,428,296 17,713,184
Ontology pays for itself. Five facts about a cheetah are returned when only one was ever stored — the rest inherited through cheetah → mammal → animal for 12K MACs. Every edge walked is a 29.8M-MAC wake that doesn't happen. It toggles off; it defaults on.
| Claim | Status |
|---|---|
| Fabric, governor, ledger, transducer, ontology | complete · 21 tests |
| FP4 / nv4 substrate, trained from scratch | real · running |
| Architectural reduction ratios above | measured in-repo |
| Conv & transformer region backends | cost models & interfaces; capability in sibling repos |
| INT2 at 2.32 effective bits | projected arithmetic — NOT measured |
| Absolute power in watts | needs a board — Phase II |
On INT2. FP4 is viable because a higher tier holds its signposts. The same move goes one rung down: keep a ~16% high-magnitude tail at FP4, crush the remaining 84% to 2 bits, for 0.16×4 + 0.84×2 = 2.32 effective bits and a further 42% cut. A first attempt has not demonstrated it. If an FP4 anchor proves too thin, FP8 signposts give 2.96 bits at a known cost. Both rungs are stated as arithmetic in the source so the projection can be checked. Neither is claimed as a result.